Automatic Generation of ACM Design-Oriented Models for MOS Transistors from Quasi-Static Wafer-Level Characterization Data

This paper introduces a novel MOS Transistor model extraction methodology from wafer-related parametric test data to characterize process variation effects. This approach provides critical insights into the impact of variability on devices after production and supports a more efficient and comprehensive design process by enabling circuit post-fabrication simulation and calibration. By identifying performance variation causes at the transistor level, the application of this method to performance prediction represents a major advancement over existing post-fabrication simulation approaches, enabling potential improvements in production yield.