A Low-Cost Open-Loop Fractional Output Divider for Audio System-on-Chip in 180 nm CMOS

This paper introduces a <inline-formula id="M1"> <math id="mathml_M1" display="inline" overflow="scroll"><mrow class="MJX-TeXAtom-ORD"><mi mathvariant="normal">Δ</mi><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mo>−</mo></mrow></mrow><mi mathvariant="normal">Σ</mi></mrow></math></inline-formula> fractional output divider (FOD) designed for audio system-on-chip (SoC) applications with low design and implementation cost. In contrast to conventional FOD design methodologies that utilize a multi-modulus divider (MMD) or a multi-phase multiplexer (MPM) based divider incorporating complex jitter filters, the proposed FOD adopts a feed-forward architecture employing simple circuit building blocks. It leverages a <inline-formula id="M2"> <math id="mathml_M2" display="inline" overflow="scroll"><mrow class="MJX-TeXAtom-ORD"><mi mathvariant="normal">Δ</mi><mrow class="MJX-TeXAtom-ORD"><mo>−</mo></mrow><mi mathvariant="normal">Σ</mi></mrow></math></inline-formula> digital-to-frequency converter (DFC) to generate fractionally synthesized output frequencies, eliminating the synchronous constraint associated with MMD and MPM methods. The DFC employs a fully-synthesizable <inline-formula id="Z-20250923154600"> <math id="mathml_Z-20250923154600" display="inline" overflow="scroll"><mi mathvariant="normal">Δ</mi><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mo>−</mo></mrow></mrow><mi mathvariant="normal">Σ</mi></math></inline-formula> modulator and resistor-2 resistor (R-2R) digital-to-analog converter to generate 4-level waveform patterns containing the desired output frequency information. These patterns are then processed through an integrator and a zero-crossing detector to reconstruct the fractionally divided output clock signal. Furthermore, to minimize jitter, a simple edge combiner-based jitter filter is cascaded with the DFC output. Implemented in 180 nm digital complementary metal-oxide-semiconductor process and operating at 1.2 V supply voltage, the proposed FOD offers an output frequency range of 500 kHz to 45 MHz, with <inline-formula id="M4"> <math id="mathml_M4" display="inline" overflow="scroll"><mrow class="MJX-TeXAtom-ORD"><msub><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi>N</mi></mrow></mrow><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi mathvariant="normal">m</mi><mi mathvariant="normal">i</mi><mi mathvariant="normal">n</mi></mrow></mrow></mrow></msub><mo>=</mo><msub><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi>F</mi></mrow></mrow><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi mathvariant="normal">I</mi><mi mathvariant="normal">N</mi></mrow></mrow></mrow></msub><mrow class="MJX-TeXAtom-ORD"><mo>/</mo></mrow><msub><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi>F</mi></mrow></mrow><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mrow class="MJX-TeXAtom-ORD"><mi mathvariant="normal">O</mi><mi mathvariant="normal">U</mi><mi mathvariant="normal">T</mi></mrow></mrow></mrow></msub><mo>=</mo><mn>4</mn></mrow></math></inline-formula>. Specifically, It divides a 26 MHz input to generate a 6.144 MHz (128fs = 128 × 44.1 kHz) output, exhibiting a root-mean-square jitter of 3.68 ps, while consuming 0.22 mW of power.