Real-time power loss optimized operation of a solid state transformer by utilizing the common-mode voltage

This article presents a general methodology and a real-time capable, analytically solvable model for minimizing the total power losses of a modular Solid-State Transformer (SST). The approach leverages the inherent Degree of Freedom (DoF) offered by the common-mode (CM) voltage u cm in three-phase systems. By systematically adjusting the CM voltage, the power distribution among all sub-modules (SM) is influenced to reduce the total losses of the Dual Active Bridges (DAB) without imposing additional constraints on the SST operation. An analytical loss model, with the CM voltage as the DoF, is derived from measured loss characteristics of an individual DAB module and extrapolated to the full three-phase SST. The proposed optimization method is implemented on a field-programmable gate array which is able to find the global loss minimum in real time. A 45 kW, 400 V AC to 750 V DC SST test bench is used to validate the methodology. The calculated and measured results over the whole power range of the prototype align which confirms the accuracy of the loss model. An overall loss reduction of up to 20% is achieved without sacrificing output voltage quality or requiring changes to the modulation scheme. • We measured and fitted the losses of a Solid-State-Transformer (SST) sub-module. • These loss functions are combined to estimate the power losses of an SST phase. • A real-time common-mode voltage (CMV) optimizer is implemented on an FPGA. • The optimizer calculates the optimal CMV to minimize the SST losses. • Measurements show that using the CMV reduces losses by up to 20%.