A Compiled 7th-order Leapfrog ADC in 130 nm CMOS

Abstract This paper presents the design and implementation of a 7th-order Leapfrog analog-to-digital converter (ADC). Each integrator of the 7th-order continuous-time (CT) filter is stabilized by local digital feedback with a single-bit quantizer, making the entire ADC as stable as a first-order continuous-time sigma-delta modulator (CT- $$\Sigma \Delta$$ M). Without sacrificing stability, the high filter order enables a low oversampling ratio (OSR) and provides excellent anti-alias filtering. The modular structure and low design complexity of the Leapfrog ADC make it particularly suitable for programmatic design methodologies. We demonstrate this through a custom Python-based layout compilation tool that generates the entire ADC layout from source code. Implemented in 130 nm CMOS, the prototype achieves 82 dB dynamic range and consumes 2.5 mW from a 1.5 V supply. The measured alias rejection exceeds 88 dB for signals in the 21–23 MHz band around the 22 MHz sampling frequency.