Design of a low-power hybrid adder with reduced delay using a conditional algorithm-based behavioral model

This paper examines self-switching for the function of a full adder, a fundamental block used in building a circuit to count one’s circuit using a conditional algorithm. The primary objective of the proposal is to minimise logic delay and net delay, thereby achieving the specific functionality and reducing static and dynamic power consumption, without compromising circuit performance. The self-switch-based method saves 25% on-chip power, and the dynamic power concern saves 17% for counting one’s circuit using the commercial tool of Xilinx Vivado. The proposed design simulation is based on the system Verilog with universal verification methodology to optimize the conditional algorithm for self-switching based on the third operand input Cin to the specific function, which is more beneficial to the arithmetic and counting circuit. At the same time, Cin is a source and carry as the destination by a self-switch Conditional algorithm. The Interconnection path delay for FA is 32.396 ps, and the on-chip power is 0.872microwatt. The total path delay (including logic & net delay) based on different paths in counting one’s circuit by the proposed method reduces 14% data path delay.