Low-Power, High-Frequency Frequency Dividers Utilizing a Separated Clock and Output Production Stage TSPC Flip-Flop

This paper presents novel architectures for high-performance frequency divider circuits based on a proposed True Single-Phase Clock (TSPC) flip-flop design. The proposed TSPC flip-flop is structured into two distinct stages: a clock production stage and an output production stage, which includes a positive latch and an inverter. Leveraging this architecture, a new divider-by-2 circuit is developed that achieves superior speed and is capable of generating a square output. Previous divider-by-3 utilizing TSPC flip-flops suffer from increased power consumption due to the simultaneous activation of pull-up and pull-down transistors. A fundamental design limitation that transistor sizing partially mitigates but does not eliminate. To overcome this, the proposed divider-by-3 employs two modified TSPC flip-flops that prevent concurrent pull-up and pull-down transistor conduction, significantly reducing power consumption. Further, the modular separation of clock and output production stages enables frequency dividers for arbitrary division ratios (4, 6, 8, [Formula: see text], N). For a divider by N, one output production stage and ([Formula: see text]) positive latches operate synchronously with a common clock production stage. Each divider stage is synchronized through a shared clock production stage, enabling the positive latches and output production stage to operate independently and in parallel. This results in consistent operating frequencies across dividers, with reduced transistor count and enhanced power efficiency, making the design especially suitable for high-frequency applications. Simulations conducted using TSMC 65[Formula: see text]nm CMOS technology and HSPICE confirm the effectiveness of the proposed dividers. Operating at a supply voltage of 1.2[Formula: see text]V, the proposed circuits achieve maximum operating frequencies of up to 21[Formula: see text]GHz for the divider-by-2 and 20[Formula: see text]GHz for higher-order dividers. The power consumption of the dividers for divider-by-2, divider-by-3 (employing the proposed TSPC), divider-by-4, divider-by-6 and divider-by-8 is measured at 102[Formula: see text][Formula: see text]W, 122[Formula: see text] [Formula: see text]W, 95.7[Formula: see text] [Formula: see text]W, 97[Formula: see text] [Formula: see text]W and 97.3[Formula: see text] [Formula: see text]W, respectively.