Usage of Low‐Cost Auxiliary Moduli for Optimization of Modular Exponentiation Operations

ABSTRACT For the implementation of modular operations in hardware description languages, the native operator is widely used due to its simplicity. However, this work proposes dedicated modular multipliers using a compressor placement strategy similar to the Wallace approach, maximizing the number of compressors per iteration. The performance of the native modular operator and the proposed iterative solution are compared, including their behavior under different modulus types. We also demonstrate that although moduli of the form generally perform worse than or , they can be converted into auxiliary moduli with improved performance through a simple modular correction step. The proposed approach achieved an average delay reduction of in modular exponentiation operations, particularly relevant for cryptographic applications. Furthermore, FPGA synthesis on an Altera MAX 10 device confirmed the practical viability of the method, with fully combinational single‐cycle multipliers reaching throughputs of up to 640 MB/s—surpassing several recent state‐of‐the‐art designs in the literature.