The NorthPole Validator: A Cycle-Accurate Simulator for HW/SW Codesign of a Prescheduled Neural Inference Accelerator
This is a case study of how NorthPole, a neural inference accelerator with a highly novel architecture, was designed, verified, and fabricated successfully in first-silicon using a horizontally integrated design workflow centered on a cycle-accurate functional simulator called the NorthPole Validator. The Validator is NorthPole’s digital twin. The study demonstrates how the Validator’s scalable network-of-queues structure, consisting of approximately 26,000 nodes and 415,000 queues, let it easily pivot from architecture validation and compiler codesign, to logic and physical design verification, post-silicon testing, and software ecosystem development.
Authors
- Filipp Akopyan (ORCID: https://orcid.org/0009-0001-5312-1311)
- Myron Flickner
- Rathinakumar Appuswamy
- Michael DeBole (ORCID: https://orcid.org/0000-0002-3068-9430)
- Brian Taba (ORCID: https://orcid.org/0009-0008-7831-1139)
- W. P. Risk (ORCID: https://orcid.org/0009-0004-3211-0738)
- Andrew S. Cassidy (ORCID: https://orcid.org/0000-0001-7305-4198)
- Nathaniel J. McClatchey
- Dharmendra S. Modha (ORCID: https://orcid.org/0009-0005-6714-8127)
- Pallab Datta (ORCID: https://orcid.org/0000-0002-0515-9729)
- Carlos Ortega Otero
- Jeffrey A. Kusnitz
- Jun Sawada
- John V. Arthur
- Alexander Andreopoulos (ORCID: https://orcid.org/0009-0001-2408-5171)
- Tapan K. Nayak (ORCID: https://orcid.org/0000-0001-8941-8961)
- Daniel F. Smith
Publication Details
- Published
- 2025-09-15
- DOI
- https://doi.org/10.1109/hpec67600.2025.11196225
- Primary Topic
- Neural Networks and Applications
- Type
- article
- Field-Weighted Citation Impact
- 0.00