Towards an Algorithm-based Approach for Soft Error Tolerance using Interval Arithmetic

Soft errors pose a critical reliability concern for modern electronics both in space and terrestrial applications. The traditional hardware redundancy approaches such as triple modular redundancy or dual modular redundancy introduce significant overheads, especially in large modern SoCs which must consider tradeoffs between power, performance, area, and reliability requirements. We propose a new approach for hardware redundancy based on the ideas behind algorithm-based fault tolerance (ABFT). Rather than replicating entire logic modules in the design, we propose using floating-point interval arithmetic to realize redundancy in computational datapaths. Error detection is then performed by leveraging the guarantees provided by interval arithmetic and forward error analysis of the specific algorithm. We demonstrate the technique for protection of a hardware FFT datapath and a systolic array. To evaluate the approach, a silicon test chip is fabricated in a 28nm process and post-PnR/simulation results demonstrate up to 2-3 times savings in area.