NTT-SAA: Exploring NTT Acceleration with 2-D Systolic Array Architecture on FPGAs

Number Theoretic Transform (NTT) is a key operation for efficient polynomial multiplication in lattice-based cryptographic schemes. This paper explores using a 2-D Systolic Array Architecture (SAA) for accelerating the NTT. The architecture offers inherent regularity, scalability, and flexibility, allowing it to support various polynomial sizes without requiring modifications to the design. Specifically, we introduce a formal methodology for mapping the NTT computation onto a 2-D systolic array, considering small array sizes to ensure scalability. To support the mapping, we design a novel processing element that efficiently enables tile-based computation. In addition, we develop a performance model and conduct Design Space Exploration (DSE) to identify optimal array dimensions. Guided by the DSE insights, we implement the accelerator, named NTT-SAA, for different polynomial sizes. Evaluation results show that the NTT-SAA family can achieve 1.4×–2.1× speedups across various Post-Quantum Cryptography (PQC) protocols while maintaining a comparable Area-Time Product (ATP) to state-of-the-art designs.