Easy Acceleration with Distributed Arrays

High level programming languages and GPU accelerators are powerful enablers for a wide range of applications. Achieving scalable vertical (within a compute node), horizontal (across compute nodes), and temporal (over different generations of hardware) performance while retaining productivity requires effective abstractions. Distributed arrays are one such abstraction that enables high level programming to achieve highly scalable performance. Distributed arrays achieve this performance by deriving parallelism from data locality, which naturally leads to high memory bandwidth efficiency. This paper explores distributed array performance using the STREAM memory bandwidth benchmark on a variety of hardware. Scalable performance is demonstrated within and across CPU cores, CPU nodes, and GPU nodes. Horizontal scaling across multiple nodes was linear. The hardware used spans decades and allows a direct comparison of hardware improvements for memory bandwidth over this time range; showing a 10x increase in CPU core bandwidth over 20 years, 100x increase in CPU node bandwidth over 20 years, and 5x increase in GPU node bandwidth over 5 years. Running on hundreds of MIT SuperCloud nodes simultaneously achieved a sustained bandwidth >1 PB/s.

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Publication Details

Published
2025-09-15
DOI
https://doi.org/10.1109/hpec67600.2025.11196478
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
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article

Easy Acceleration with Distributed Arrays

Albert Reuther, Michael E. Houle, William Arcand, Vijay Gadepally et al.
Embedded Systems Design Techniques
article

Easy Acceleration with Distributed Arrays

Albert Reuther, Michael E. Houle, William Arcand, Vijay Gadepally, Ryan Haney, Lauren Milechin, Michael T. Jones, Julie Mullen, William Bergeron, Hayden Jananthan, Jeremy Kepner, David Bestor, Piotr Łuszczek, Matthew Hubbell, Chansup Byun, Guillermo Morales, Daniel Burrill, Andrew Prout, Antonio Rosa, Larry W. Anderson, Charles Yee, Peter Michaleas, Alex Bonn
article en

Abstract

High level programming languages and GPU accelerators are powerful enablers for a wide range of applications. Achieving scalable vertical (within a compute node), horizontal (across compute nodes), and temporal (over different generations of hardware) performance while retaining productivity requires effective abstractions. Distributed arrays are one such abstraction that enables high level programming to achieve highly scalable performance. Distributed arrays achieve this performance by deriving parallelism from data locality, which naturally leads to high memory bandwidth efficiency. This paper explores distributed array performance using the STREAM memory bandwidth benchmark on a variety of hardware. Scalable performance is demonstrated within and across CPU cores, CPU nodes, and GPU nodes. Horizontal scaling across multiple nodes was linear. The hardware used spans decades and allows a direct comparison of hardware improvements for memory bandwidth over this time range; showing a 10x increase in CPU core bandwidth over 20 years, 100x increase in CPU node bandwidth over 20 years, and 5x increase in GPU node bandwidth over 5 years. Running on hundreds of MIT SuperCloud nodes simultaneously achieved a sustained bandwidth >1 PB/s.

Moscow Institute of Thermal Technology (RU)
Openalex Percentile: Top 68%
Embedded Systems Design Techniques
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