On the Adaptation of Mixed-Radix Fast Fourier Transform for Resource-Constrained Environments

Mission-critical edge applications often demand FFTs under the stringent constraints of performance, accuracy, and power. With many vendor FFT libraries only supporting power-of-two FFTs, the need for zero-padding of non-power-of-two inputs to facilitate the use of power-of-two FFT libraries can degrade accuracy by introducing spectral artifacts and increase power consumption by unnecessarily computing on zeroes. Furthermore, striking the right balance between performance, accuracy, and power can significantly impact developer productivity and, in turn, delay deployment.To address the limitations imposed by these constraints, we realize a mixed-radix FFT (MR-FFT) for 1,600-and 8,000-point inputs on a low-power FPGA that uses a high-level synthesis approach to enable efficient design exploration. Specifically, our MR-FFT on a krtkl Snickerdoodle board, which features an ARM Cortex-A9 CPU and Xilinx Artix-7 FPGA, (1) maintains or improves accuracy when compared to power-of-two FFT with zero-padding, (2) achieves 2.5× lower power consumption and 1.3× better energy efficiency over a Raspberry Pi CM5 GPU, and (3) delivers an average of 4.9× speedup over the NumPy FFT implementation on the Cortex-A9 CPU.