Evaluating AMD-Xilinx Frameworks for Deep-Learning Acceleration on Versal
AMD-Xilinx Versal Adaptive System-on-Chip devices are powerful hardware accelerators with a variety of tools for implementing high-performance, low-power, deep-learning models. Vitis AI, a machine-learning framework created by AMD-Xilinx, accelerates deep-learning algorithms using the Deep-Learning Processor Unit (DPU), which includes a Versal-specific architecture designed to take full advantage of the unique processing elements on select Versal platforms. However, the DPU does not run efficiently for small models due to its general-purpose nature. FINN, another machine-learning framework created by AMD-Xilinx, complements Vitis AI by providing custom low-latency, high-throughput accelerators for highly quantized networks. Due to the Versal’s incompatibility with FINN’s software drivers, FINN has not yet been tested on Versal hardware against Vitis AI. In this research, we create a novel custom wrapper and driver to allow FINN accelerators to run efficiently on Versal devices. We also add preprocessing to the generated FINN accelerator to avoid bottlenecks at high levels of parallelization. We use this adjusted accelerator and wrapper to directly compare Vitis AI’s DPU against FINN-created accelerators on the Versal AI Core across two deep-learning classification models in terms of throughput, power efficiency, and device utilization. We found that for a small convolutional model designed in the original FINN research, FINN achieves a speedup of 10.1× over a DPU architecture that consumes a similar amount of power. Running MobileNetV1, the most performant (highest framerate) DPU tested achieves a speedup of 3.0× compared to the most performant FINN architecture tested, but consumes significantly more power (40.8 W vs 17.8 W). From our results, we conclude that FINN can offer better performance and power efficiency for small models and can be used as a low-power alternative to Vitis AI’s DPU on larger edge-computing models such as MobileNetV1.
Authors
- Alan D. George (ORCID: https://orcid.org/0000-0001-9665-2879)
- Peter Drum
Institutions
- Computing Center (RU)
Publication Details
- Published
- 2025-09-15
- DOI
- https://doi.org/10.1109/hpec67600.2025.11196474
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00