Investigation on the Interference of Floating Charge With the Effectiveness of ESD Bus-Based Clamp Network

This study investigates a floating electrostatic discharge (ESD) bus-based clamp network with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i>-triggered n-type lateral diffusion MOSFET (nLDMOS), designed for robust and area-efficient ESD protection in multiple high-voltage open-drain outputs. However, several unreported abnormal ESD behaviors, which significantly compromise protection effectiveness, have been discovered, including trigger delay, clamp voltage shift, and premature thermal failure. These behaviors stem from accumulated charges at the floating ESD bus, which suppress the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> coupling effect and prevent the nLDMOS from fully conducting. The transmission line pulse (TLP) characterization with varying TLP/dc pulse intervals revealed the correlation between floating charge dynamics and these abnormal behaviors. Furthermore, both controlled light illumination and extended TLP/dc measurement intervals can benefit the leakage current formation and suppress floating charge accumulation, thereby ensuring proper ESD functionality of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i>-nLDMOS as per design expectation. This work first reveals the issue of protection effectiveness associated with floating charge dynamics in high-voltage (HV) ESD engineering and provides essential insights into mitigating their impact, which may offer a fundamental design consideration for high-voltage ESD engineers.