STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration

Chiplet-based architectures and advanced packaging have emerged as transformative approaches in semiconductor design. While conventional physical design for 2.5D heterogeneous systems typically prioritizes wirelength reduction through tight chiplet packing, this strategy introduces thermal bottlenecks and intensifies coefficient of thermal expansion (CTE) mismatches, compromising long-term reliability. Addressing these challenges requires holistic consideration of thermal performance, mechanical stress, and interconnect efficiency. We introduce STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D integration, the first automated placement methodology that simultaneously optimizes these critical factors. Our approach employs finite element analysis to simulate temperature distributions and stress profiles across chiplet configurations while minimizing interconnect wirelength. Experimental results demonstrate that a thermal and structurally aware automated placement approach reduces overall stress by 11 %, maintains excellent thermal performance with a negligible <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{0. 5 \%}$</tex> temperature increase and simultaneously reduces total wirelength by 11 % compared to temperature-only optimization. Additionally, we conduct an exploratory study on the effects of temperature gradients on structural integrity, providing crucial insights for reliability-conscious chiplet design.