LHAM: Low-Cost and High-Accuracy Approximate Multiplier for FPGA-Based Computing

The rapid development of artificial intelligence raises higher demands on the performance of intelligent devices, requiring new computing units with lower resource usage and power consumption. Approximate Multipliers (AMs) meet this need by reducing resource and power consumption at the cost of computational accuracy and are widely used in fields like image processing and deep neural networks. In this article, we present a Low-Cost and High-Accuracy Approximate Multiplier (LHAM) design methodology targeting Field Programmable Gate Arrays (FPGAs). The expressions of carry propagation and carry generation for FPGA-based Carry-Look-Ahead Adders (CLA) are optimized, which effectively reducing the errors associated with discarding carry generation information. Using these expressions together with a logic fusion based approximation strategy, we design both accurate and approximate adders. These adders can be selectively configured during the partial product accumulation stage of the multiplier, allowing a tunable tradeoff between computational accuracy and hardware resource utilization. Finally, we model the AM design space as a 0-1 Knapsack problem to efficiently generate optimized designs under varying accuracy and area requirements. Experimental results show that, compared to the Xilinx accurate multiplier IP core, the proposed LHAM reduces LUT usage, delay, and power consumption by 50.7%, 21.7%, 20.6% for \(8\times 8\) multiplication, respectively. Compared to existing AMs, LHAM uses the fewest LUTs and achieves the best tradeoff between accuracy and area. The proposed LHAM is also applied to two applications to demonstrate its efficiency and effectiveness.