Exploration and Insights into Vertical Nanowire/sheet FETs for Ultimate Scaled Circuits/Systems

We report on nanowire (NW)/nanosheet (NS) FETs with vertical transport (VFET) that can enable ultra scaled circuits/systems and be introduced on the wafer’s frontside (FS) or/and backside (BS). A thorough performance evaluation of (un)doped Si vertical channel devices built with a simple self-aligned spacers scheme is presented, used to avoid DC impact from a vertical misalignment of the gate electrode towards the pillar’s top/bottom highly doped SiGe source (S)/drain (D) areas. Optimal S/D access configuration is determined for various processes and layouts of bottom, top electrodes (BE,TE), with no significant impact seen on noise or reliability. Junctionless (JL) VFETs also show suitability to operate in a large temperature range with better electrostatics for 300K→20K, and noise values slightly increasing down to 60K at |VG-VT|=0-0.2V. For SoC hotspot mitigation, VFET architecture allows further options for improved thermal management at no footprint cost, e.g., use of longer (taller) Lgate, thicker spacers, merged S/D epi for the device’s array pillars.