Dead-Time Optimization Strategy for Asymmetric CLLC Resonant Converters

The asymmetric CLLC resonant converter has been extensively studied due to its excellent symmetric bidirectional power transfer capability and high power density. Conventional studies on asymmetric CLLC resonant converters have primarily focused on parameter optimization and wide voltage range design, with an emphasis on achieving zero-voltage switching (ZVS) of the primary-side MOSFETs during the dead-time. However, the conduction loss of body diodes is frequently neglected, significantly compromising converter efficiency. To address this issue, this paper proposes a dead-time optimization strategy for asymmetric CLLC resonant converters. The dead-time is dynamically tuned according to the operational dynamics of the CLLC resonant converter, eliminating primary-side body diode conduction losses without compromising ZVS attainment. Experimental validation demonstrates that the proposed dead-time optimization strategy achieves a $0.61 \%$ improvement in peak efficiency, confirming the theoretical analysis.