A Common-Mode Voltage Suppression Strategy Based on the Three-Phase Four-Leg Inverter

This paper proposes an improved three-dimensional space vector pulse width modulation (3D-SVPWM) strategy, implemented directly in the abc coordinate system, to suppress common-mode voltage in a three-phase four-leg inverter. First, the inverter topology is analyzed to identify the sources of common-mode voltage. Then, based on the distribution characteristics of voltage space vectors in the abc frame, a novel vector selection method is introduced. Instead of using conventional zero vectors, a nearby non-zero vector in the opposite direction of the reference vector is selected. This approach reduces the amplitude of the output common-mode voltage while maintaining low control complexity. Finally, simulation results verify that the proposed strategy effectively suppresses common-mode voltage and remains robust under load imbalance conditions.