A Dual-Path Topology for Single-Inductor Dual-Output DC–DC Converters

This article presents a high-efficiency, high-power-density single-inductor dual-output (SIDO) converter based on a dual-path (DP) topology. The proposed DP-SIDO converter supports a theoretical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\sim 1$</tex-math> </inline-formula> voltage conversion ratio (VCR) and arbitrary load differences and introduces three key advantages. First, both the dc and ripple currents through the inductor are significantly reduced, enabling the use of a smaller inductor and enhancing efficiency. Second, the reduced inductor current decreases the discontinuous current through energy allocation switches, thereby reducing the voltage spikes and enhancing reliability. Third, because the inductor and the flying capacitors alternately deliver current to the outputs, the output voltage ripple can be reduced. A dedicated DP-SIDO control strategy is also proposed to provide the fast transient response and minimal cross regulation. Fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process with all power transistors integrated on-chip, the proposed converter demonstrates the highest efficiency of 94.5% among previous single-inductor multiple-output (SIMO) converters under similar VCR conditions and delivers 4-A total load current with a compact inductor measuring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times 2.5\times 1.2$</tex-math> </inline-formula> mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>. For a 1.6-A load step on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {o2}}$</tex-math> </inline-formula> with a 200-ns rise time, the measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {O2}}$</tex-math> </inline-formula> undershoot is only 136 mV, and the cross regulation is as low as 7 mV/A.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-10-15
DOI
https://doi.org/10.1109/jssc.2025.3618166
Primary Topic
Advanced DC-DC Converters
Type
article
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article

A Dual-Path Topology for Single-Inductor Dual-Output DC–DC Converters

Baochuang Wang, Lin Cheng, Minghao Shang
IEEE Journal of Solid-State Circuits
Advanced DC-DC Converters
article

A Dual-Path Topology for Single-Inductor Dual-Output DC–DC Converters

Baochuang Wang, Lin Cheng, Minghao Shang
article en

Abstract

This article presents a high-efficiency, high-power-density single-inductor dual-output (SIDO) converter based on a dual-path (DP) topology. The proposed DP-SIDO converter supports a theoretical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\sim 1$</tex-math> </inline-formula> voltage conversion ratio (VCR) and arbitrary load differences and introduces three key advantages. First, both the dc and ripple currents through the inductor are significantly reduced, enabling the use of a smaller inductor and enhancing efficiency. Second, the reduced inductor current decreases the discontinuous current through energy allocation switches, thereby reducing the voltage spikes and enhancing reliability. Third, because the inductor and the flying capacitors alternately deliver current to the outputs, the output voltage ripple can be reduced. A dedicated DP-SIDO control strategy is also proposed to provide the fast transient response and minimal cross regulation. Fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process with all power transistors integrated on-chip, the proposed converter demonstrates the highest efficiency of 94.5% among previous single-inductor multiple-output (SIMO) converters under similar VCR conditions and delivers 4-A total load current with a compact inductor measuring <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times 2.5\times 1.2$</tex-math> </inline-formula> mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>. For a 1.6-A load step on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {o2}}$</tex-math> </inline-formula> with a 200-ns rise time, the measured <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {O2}}$</tex-math> </inline-formula> undershoot is only 136 mV, and the cross regulation is as low as 7 mV/A.

IEEE Journal of Solid-State CircuitsVol. 61(3)
University of Science and Technology of China (CN)
Openalex Percentile: Top 71%
Advanced DC-DC Converters
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