Efficient Parallel Testing and Implicit Cost-Driven Tuning of RF-MIMO Systems
Modern wireless communications systems deploy massive MIMO systems with large numbers of transmit and receive antennas and analog–digital RF transceiver architectures that admit RF beamforming. These systems need to be tested and tuned postmanufacture to ensure signal quality. In analog architectures, this poses a problem due to the lack of observability of internal circuit nodes and due to the convergence of multiple RF beamforming chains into a combined baseband signal from which it is difficult to de-embed individual RF chain behaviors. Existing test techniques estimate nonlinearities in RF chains up to the third order and require significant frequency bandwidth to test multiple RF chains in a MIMO system in parallel, thereby reducing the overall test time. In this research, to improve testing efficiency, overlapping test tones over a minimal frequency range are applied to each of the MIMO RF chains in parallel, allowing specifications of individual RF chains up to fifth-order distortion to be determined accurately. For postmanufacture tuning, a response feature clustering approach followed by an implicit cost-driven tuning procedure is proposed. Tuning for error vector magnitude (EVM) and signal-to-interference ratio (SiNR) is performed under power constraints. Experimental results show that the proposed parallel testing methodology is 1.7<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\times$</tex-math></inline-formula> more frequency-efficient than existing techniques, and the proposed postmanufacture tuning algorithm can tune a receiver with four RF chains in 1.8 ms.
Authors
- Suhasini Komarraju (ORCID: https://orcid.org/0000-0001-6480-038X)
- Sabyasachi Deyati (ORCID: https://orcid.org/0000-0001-9172-2495)
- Abhijit Chatterjee (ORCID: https://orcid.org/0000-0003-1553-4470)
Institutions
- Georgia Institute of Technology (US)
- Intel (United States) (US)
Publication Details
- Journal
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Published
- 2025-10-15
- DOI
- https://doi.org/10.1109/tvlsi.2025.3526125
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00