Power-Clamp-Triggered SCR for Broadband RF ESD Protection

A compact electrostatic discharge (ESD) protection circuit using silicon-controlled rectifiers (SCRs) for radio frequency (RF) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>/O interfaces is proposed and implemented in the TSMC 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m CMOS process. The design ensures robust ESD protection by enabling discharge through multiple paths between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>/O pins and power rails. To mitigate the parasitic capacitance introduced by the SCRs, an inductor is integrated for compensation. As a result, the proposed circuit achieves comprehensive ESD protection while preserving high signal integrity and minimizing chip area, making it a highly efficient solution for high-frequency applications.

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Publication Details

Journal
IEEE Transactions on Electron Devices
Published
2025-10-14
DOI
https://doi.org/10.1109/ted.2025.3617031
Citations
2
Primary Topic
Electrostatic Discharge in Electronics
Type
article
Field-Weighted Citation Impact
1.46
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article

Power-Clamp-Triggered SCR for Broadband RF ESD Protection

Chun‐Yu Lin, Hong Cheng
2 citations
IEEE Transactions on Electron Devices
Electrostatic Discharge in Electronics
1.46
article

Power-Clamp-Triggered SCR for Broadband RF ESD Protection

Chun‐Yu Lin, Hong Cheng
article en
2 citations

Abstract

A compact electrostatic discharge (ESD) protection circuit using silicon-controlled rectifiers (SCRs) for radio frequency (RF) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>/O interfaces is proposed and implemented in the TSMC 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m CMOS process. The design ensures robust ESD protection by enabling discharge through multiple paths between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$</tex-math> </inline-formula>/O pins and power rails. To mitigate the parasitic capacitance introduced by the SCRs, an inductor is integrated for compensation. As a result, the proposed circuit achieves comprehensive ESD protection while preserving high signal integrity and minimizing chip area, making it a highly efficient solution for high-frequency applications.

IEEE Transactions on Electron DevicesVol. 72(12)
National Taiwan Normal University (TW), National Yang Ming Chiao Tung University (TW)
Openalex Percentile: Top 15%
Electrostatic Discharge in Electronics
1.46
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