Enabling Low-Complexity Massive MIMO Detection Using In-Memory Computing

Massive multiple-input multiple-output (MIMO) is a key technology in modern wireless communication systems, offering significant improvements in spectral efficiency, capacity, and reliability. However, the computational complexity of massive MIMO detection remains a major challenge, particularly for energy-efficient hardware implementations. This paper explores a novel approach to implementing a massive MIMO detector using in-memory-computing (IMC) technology, which reduces data movement overhead and enhances computational efficiency. We present a low-complexity hardware architecture that leverages in-memory computation to accelerate MIMO detection while minimizing power consumption. Analytical results demonstrate that the proposed IMC-based massive MIMO detector achieves significant performance gains in terms of throughput, latency, and energy efficiency compared to conventional architectures. Our findings highlight the potential of IMC-based approaches for next-generation wireless communication systems, paving the way for efficient and scalable massive MIMO implementations.