Robust cascade control for variable dimension systems - Application to processors’ power capping

Power savings is a key research topic in High Performance Computing (HPC). We present a control-based approach to regulate the power usage of an HPC application while maintaining its performance. Power capping is performed using the RAPL (Running Average Power Limit) actuation and sensing mechanism, which is known to have noise and inaccuracies. The Actuation is performed at the processor level, and since the number of processors in an HPC setup can vary, this results in a variable number of power signals for the same input. To Address these challenges of noise, actuator inaccuracies, and variable signal dimensions, our approach incorporates a cascade control design with robust controllers. One controller monitors real-time progress of the application and dynamically applies power caps via the RAPL actuator; the other controller adjusts the actuator’s power cap value, which we found to be inaccurate in meeting the commanded power limit. Additionally, we use a robust control approach to tune the controllers, where the PI parameters are selected to meet ℋ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</inf> performance criteria. This balances robustness and disturbance rejection, ensuring stability and performance under varying conditions. This approach provides a robust solution to power control in the presence of system uncertainties. The experiments run the Embarrassingly Parallel (EP) compute-intensive HPC benchmark on various clusters of the Grid’5000 platform. Using this approach, we improved RAPL accuracy and reduced the power consumption by 25%, with a trade-off of a 10% reduction in performance.