A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET

This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8 \times 8$</tex-math> </inline-formula>) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same first-rank interleaver, share the identical injection-locked ROSC (IROSC) for voltage-to-time conversion (VTC). The DMT digital signal processor (DSP) achieves optimal bit and power loading with 63 orthogonal subchannels by employing a 64-way single-stage multi-path delay feedback (MDF) fast Fourier transform (FFT) core. An on-chip sign-sign least mean square (SS-LMS) engine adapts equalizer coefficients to combat channel fluctuation. The RX prototype demonstrates 4E-4 BER when communicating over the channel, exhibiting 18-dB insertion loss (IL) at Nyquist, while consuming 347-mW power and 0.242-mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> silicon area.