Efficient computation alternatives for IEC 61000-4-30 supraharmonic quasi-peak detector

This paper proposes alternate functions and algorithms to compute the diode model of the quasi-peak detector (QPD) recently included in the IEC 61000-4-30 standard. A set of 6 best-fit equations has been identified and parametrized to avoid the trigonometric function evaluation required by the original IEC quasi-peak (QP) receiver. These functions have been run bare metal on a system-on-chip (SoC) processor and have reduced time computation by up to 80% for this QPD assessment. Moreover, two versions of the coordinate rotation digital computer (CORDIC) algorithm are explored to compute the detector with precision under 1% compared to the reference IEC QPD. This algorithm has been run on the field programmable gate array (FPGA) from the same SoC and has been shown to have the lowest latency, resource consumption, and iteration bound.