High performance and low leakage heterojunction 10 nm PZT NC-FinFET for low power application

Increasing transistor integration density and increased power are the significant challenges for designers at lower transistor technology nodes. However, scaling down the transistor leads to the uneven change in threshold voltage with scaled supply voltage, resulting in increased subthreshold conduction. So, there is a need for new materials and architectures to explore the possibility of scaling, keeping subthreshold performance under limit. In this paper, a new heterojunction 10 nm n-channel PZT NC-FinFET with Si-SiGe interface is designed and its performance is evaluated for a low-power digital circuit. The heterojunction formed between Si and SiGe, introducing a 2 nm layer of negative capacitance material over SiO_2, that offers high off-sate potential barrier, results in low leakage current and static power consumption compared to conventional FinFET. The performance of the proposed device is compared with existing FinFET with high-K dielectric in terms of drain current, electric field, channel potential, energy band, transconductance and gate capacitance. The proposed device shows a good switching current ratio I_on/I_off of 10⁹, high transconductance of 1.73 × 10⁻⁶ A/V, ideal gate capacitance and good control on subthreshold parameters, subthreshold slope (SS) ranging 30.5 mV/dec to 55.54 mV/dec. Further, p-channel NC-FinFET is also explored to check the CMOS compatibility of both n-and p-channel PZT NC-FinFET by matching their drain current characteristics and analysis through using 3D Visual TCAD tool.