Interfacial p-Si doped InZnO ferroelectric FET for enhanced memory window

Since abundant electrons serve as the primary carriers in n-type oxide semiconductors, dipole-induced electron repulsion is ineffective in increasing the threshold voltage (VT) of oxide channel ferroelectric field-effect transistors (FeFETs), thereby limiting the memory window (MW). To effectively suppress electron participation, we introduce a p-type Si (p-Si) doping technique into the InZnO (IZO) channel through co-sputtering. When the optimal p-Si condition, controlled by adjusting sputtering power, is applied, the remanent polarization obtained from positive-up, negative-down measurements increases to ∼18 μC/cm2 in the HfZrO/p-Si-doped IZO (p-Si:IZO) capacitor. This indicates that the number of electrons in p-Si:IZO, which can pin dipoles, is reduced. This electron annihilation is evidenced by lowered current drivability and an enlarged VT in an oxide transistor with a Mo/HfO2/p-Si:IZO gate stack. However, bulk p-Si doping causes charge trapping in p-Si:IZO FeFETs, restricting MW expansion. To mitigate this trade-off, p-Si doping is selectively performed only at the IZO interface. Consequently, interfacial p-Si:IZO FeFETs exhibit an MW of 2.3 V—twice that of IZO FeFETs—and 1.5 V in DC double-sweep and AC pulse measurements, respectively.