Impact of interlayer on gate leakage during endurance fatigue of Si-channel FeFETs

This work links the charge trapping capability, gate leakage, and endurance of the gate structure of FeFET in series, conducting an in-depth study of the effects of both the material properties of the interlayer and its insertion location within the gate stack on the electrical characteristics of hafnium-based ferroelectric field transistors (FeFETs). We designed two groups of experiments: one group of devices uses three different interlayers (SiOx, Al2O3, and SiON), and the other group of devices uses Al2O3 as the interlayer to be inserted at different positions (top interlayer, middle interlayer, and bottom interlayer). By examining interlayer materials with different properties, the relationship between charge trapping capability, gate leakage, and device endurance is elucidated. Our study shows that the endurance of FeFET is not only related to the traps at the ferroelectric/interlayer interface but also to the quality of the interlayer. What is more, we prove that tuning the insert positions of the interlayer relative to the FE layer can further improve the endurance of the device by suppressing gate leakage. Our work provides a perspective for improving the endurance of FeFETs and provides a co-optimization guideline for suppressing gate traps and gate leakage for further improving the endurance of FeFETs.