A 230-GHz 3.5-dBm Phase-Shifter-Embedded Frequency Tripler With Fundamental Voltage Tuning in 40-nm CMOS

A 230-GHz phase-shifter-embedded (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \varphi $</tex-math> </inline-formula>-embedded) frequency tripler (FT) for sub-THz phased-array applications is presented in this work. A fundamental voltage tuning (FVT) technique is proposed to address the CMOS breakdown voltage limits to shape the drain voltage waveform by adjusting the fundamental impedance, thereby lowering the drain-to-gate voltage. This allows for higher input power handling and yields a 2.5-dB increase in output power. A modified voltage-domain power series is utilized to estimate the FT’s output swing, enabling designers to assess whether the FT exceeds the breakdown limit. Moreover, the FT’s driving amplifier features <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \varphi $</tex-math> </inline-formula>-embedded impedance matching networks that can deliver over 120° phase shifting, impedance transformation, and single-ended-to-differential conversion, effectively reducing insertion loss and chip area. Fabricated in a 40-nm CMOS without ultrathick metal layers, the proposed FT provides 3.5-dBm output power and 0.5-dB conversion gain at 225 GHz, with a 3-dB bandwidth from 214 to 246 GHz. A phase-shifting range exceeding 360° is obtained across the 220–245-GHz frequency range. The FT consumes 230 mW from a 0.9-V supply. To the best of the authors’ knowledge, the proposed FT demonstrates the highest figure of merit above 200 GHz reported thus far.