A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)<10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup>. A new consecutive symbol-to-center (CSC) encoding scheme is proposed that assigns identifiable attributes to the data by moving all consecutive identical symbols (CISs) to the common-mode voltage (0 V) before transmission. Additionally, an on-chip decision-tree classifier is designed and implemented at the Rx back-end to learn both the channel and the CSC data encoding characteristics, enabling accurate detection of the original transmitted data in the presence of inter-symbol interference (ISI), with a latency of only 10 unit intervals (UIs). The decision-tree classifier operates with a low-power, feed-forward architecture without any feedback timing constraints, allowing the transceiver to communicate at 42 Gb/s with an energy efficiency of 1.43 pJ/b for compensating 26 dB loss. The proposed transceiver, fabricated in 16-nm FinFET, achieves a low energy/bit per channel loss of 0.055 pJ/b/dB, which is approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{\times }$</tex-math> </inline-formula> lower than prior conventional architectures.

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Publication Details

Journal
IEEE Journal of Solid-State Circuits
Published
2025-10-13
DOI
https://doi.org/10.1109/jssc.2025.3616072
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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article

A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

Tejasvi Anand, Ramin Javadi
IEEE Journal of Solid-State Circuits
VLSI and Analog Circuit Testing
article

A Machine Learning-Inspired PAM-4 Transceiver for Medium-Reach Wireline Links

Tejasvi Anand, Ramin Javadi
article en

Abstract

This article presents an energy-efficient machine learning-inspired PAM-4 wireline transceiver that leverages data encoding at the transmitter (Tx) and feature extraction with classification at the receiver (Rx) to compensate for channel loss ranging from 13 to 26 dB, while maintaining the bit error rate (BER)<10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-11</sup>. A new consecutive symbol-to-center (CSC) encoding scheme is proposed that assigns identifiable attributes to the data by moving all consecutive identical symbols (CISs) to the common-mode voltage (0 V) before transmission. Additionally, an on-chip decision-tree classifier is designed and implemented at the Rx back-end to learn both the channel and the CSC data encoding characteristics, enabling accurate detection of the original transmitted data in the presence of inter-symbol interference (ISI), with a latency of only 10 unit intervals (UIs). The decision-tree classifier operates with a low-power, feed-forward architecture without any feedback timing constraints, allowing the transceiver to communicate at 42 Gb/s with an energy efficiency of 1.43 pJ/b for compensating 26 dB loss. The proposed transceiver, fabricated in 16-nm FinFET, achieves a low energy/bit per channel loss of 0.055 pJ/b/dB, which is approximately <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2{\times }$</tex-math> </inline-formula> lower than prior conventional architectures.

IEEE Journal of Solid-State CircuitsVol. 61(3)
Oregon State University (US)
Openalex Percentile: Top 68%
VLSI and Analog Circuit Testing
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