FEditor: Consecutive Task Placement With Adjustable Shapes Using FPGA State Frames

Field Programmable Gate Arrays (FPGAs) are widely adopted in datacenters, where each FPGA is exclusively assigned to a task. This strategy results in significant resource waste and increased task rejections. To address this issue, placement algorithms adjust the locations and shapes of tasks based on Dynamic Partial Reconfiguration, which partitions an FPGA into multiple rectangular areas for sharing. However, existing schemes are designed for static task sets without adjustable shapes, incapable of optimizing the placement problem in datacenters. In this paper, FEditor is proposed as the first consecutive task placement scheme with adjustable shapes. It expands the planar FPGA models into three-dimensional ones with timestamps to accommodate consecutive tasks. To reduce the complexity of three-dimensional resource management, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">State Frames</i> (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SFs</i>) are designed to compress the models losslessly. Three metrics and a nested heuristic algorithm are used for task placement. Experimental results demonstrate that FEditor has improved resource utilization by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$19.8\%$</tex-math></inline-formula> and acceptance rate by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\%$</tex-math></inline-formula> compared to the referenced algorithms. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SFs</i> and the nested algorithm accelerate the task placement by up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10.26\times$</tex-math></inline-formula>. The suitability of FEditor in datacenter environments is verified by its time efficiency trends.

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Publication Details

Journal
IEEE Transactions on Parallel and Distributed Systems
Published
2025-10-13
DOI
https://doi.org/10.1109/tpds.2025.3620384
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00
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article

FEditor: Consecutive Task Placement With Adjustable Shapes Using FPGA State Frames

Keqin Li, Yanyan Li, Yawen Wang, Yu Chen et al.
IEEE Transactions on Parallel and Distributed Systems
Embedded Systems Design Techniques
article

FEditor: Consecutive Task Placement With Adjustable Shapes Using FPGA State Frames

Keqin Li, Yanyan Li, Yawen Wang, Yu Chen, Zhiqian Xu, Hai Jiang
article en

Abstract

Field Programmable Gate Arrays (FPGAs) are widely adopted in datacenters, where each FPGA is exclusively assigned to a task. This strategy results in significant resource waste and increased task rejections. To address this issue, placement algorithms adjust the locations and shapes of tasks based on Dynamic Partial Reconfiguration, which partitions an FPGA into multiple rectangular areas for sharing. However, existing schemes are designed for static task sets without adjustable shapes, incapable of optimizing the placement problem in datacenters. In this paper, FEditor is proposed as the first consecutive task placement scheme with adjustable shapes. It expands the planar FPGA models into three-dimensional ones with timestamps to accommodate consecutive tasks. To reduce the complexity of three-dimensional resource management, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">State Frames</i> (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SFs</i>) are designed to compress the models losslessly. Three metrics and a nested heuristic algorithm are used for task placement. Experimental results demonstrate that FEditor has improved resource utilization by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$19.8\%$</tex-math></inline-formula> and acceptance rate by at least <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\%$</tex-math></inline-formula> compared to the referenced algorithms. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SFs</i> and the nested algorithm accelerate the task placement by up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10.26\times$</tex-math></inline-formula>. The suitability of FEditor in datacenter environments is verified by its time efficiency trends.

IEEE Transactions on Parallel and Distributed SystemsVol. 37(1)
State University of New York (US), Beijing University of Posts and Telecommunications (CN), Hunan University (CN)
Openalex Percentile: Top 68%
Embedded Systems Design Techniques
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