High-Level Synthesis Pipeline Optimization Method for ANN Backpropagation Algorithm Using FPGA SoC

Research on the Backpropagation Artificial Neural Network (BANN) method continues to depend on generating hardware description language (HDL) directly from the algorithm. Converting the algorithm into a Hardware Description Language (HDL) that can be synthesized and implemented into a Field-Programmable Gate Array (FPGA) System-on-Chip (SoC) necessitates a complex and challenging endeavour. This study examines the outcomes of the BANN algorithm's High-Level Synthesis (HLS) on the Zynq7000 series XC7Z010CLG400-1 FPGA SoC family. Utilizing the Vivado HLS program showcases the accurate correlation between C's simulation and synthesis results, validating the consistency between the software and hardware components. The optimal optimization strategy involves utilizing feedforward connections that transmit information directly from the input to the hidden phase. The reverse stage involves adjusting the weights that connect the input unit to the hidden phase. The computational speed of the pipeline is roughly 5,340 nanoseconds (178 multiplied by 30 nanoseconds), which is 2.2 times (398 multiplied by 30 nanoseconds) quicker than the speed it would have without optimization. Approximately 55.28% of the latency, equivalent to 220 clock cycles, is reduced. The average device usage rate is 32.75%.