PCIE Physical Layer Verification using UVM

Peripheral Component Interconnect Express (PCIe) represents a high-speed, serial communication standard that operates on a point-to-point connection basis. The latest PCIe Gen5.0 specification achieves data transfer rates of 32GT/s per lane while maintaining backward compatibility with earlier generations including Gen4.0 (16GT/s), Gen3.0 (8GT/s), Gen2.0 (5GT/s), and Gen1.1 (2.5GT/s). This research focuses on validating PCIe Gen5.0 transactions occurring between the Media Access Control layer and the Physical layer, which comprises SerDes components and the Physical Media Attachment sublayer. The PCIe standard employs a hierarchical design structure consisting of three separate functional layers. Data transmission between these architectural layers is accomplished through packet-based communication mechanisms.The Universal Verification Methodology is used for development of PCIe, which is written in System Verilog (UVM) and used Cadence Xcelium Tool.