Architecture and Energy Efficiency Optimization of Neural Network Accelerator Based on RISC-V Instruction Set Extension

The escalating demand for energy efficiency in edge AI systems has spurred the development of computational architectures that integrate high precision, flexibility, and ultralow power consumption. This work proposes a RISC-V-based neural network accelerator that overcomes the inefficiency of existing solutions in executing floating-point-intensive tasks under sub-milliwatt (${\lt}1 \mathrm{~mW}$) constraints. Through synergistic optimization across instruction set architecture (ISA) and microarchitecture, coupled with circuit-level energy-efficient component design-including Booth-4 multipliers and carry-save adder (CSA) trees-a cross-layer verification framework is established to achieve a notable balance between numerical fidelity and energy efficiency. Key innovations include: an IEEE 754-compliant floating-point unit (FPU) supporting dynamic FP32/INT8 precision switching to adapt to varying computation requirements; a 13-bit Booth-4 algorithm-based multiplier that achieves a 38.5% reduction in multiply-accumulate (MAC) operation energy consumption; a 56-bit pipelined carry-save adder tree enabling a 21% reduction in dynamic power dissipation; and a two-stage fused multiply-add (FMA) pipeline enhancing computational throughput. Post-silicon validation in a 180 nm CMOS process demonstrates a total chip area of $6.90 \mathrm{~mm}^{2}$ and a system-wide power consumption of 1.28 mW, with the configurable CNN accelerator accounting for $\mathbf{6 0. 4 \%}$ of the total power budget. Real-world applications in real-time gesturecontrolled gaming and autonomous obstacle avoidance systems validate the architecture’s practical utility and robustness under strict power constraints. This work offers a scalable edge AI solution unifying programmability and ultra-low power. Future efforts target FP16/BF16 support and advanced nodes (e.g., 28nm) to optimize energy efficiency.