Chip-level pre-calibration-based calibration-free metrology technology: research on high-precision current integration and voltage circuit design consistency

This study proposes an error calibration method for user-level calibration-free metrology chips. By integrating dynamic compensation algorithms and hardware optimization during the chip testing phase, the method achieves on-chip self- calibration for current sampling and ensures theoretical-practical consistency in voltage circuit design. This approach shifts traditional user-end calibration to the chip production stage, reducing user operational complexity while maintaining accuracy within ±1% across a full temperature range. Experimental results demonstrate that system errors remain stable below 1% under wide load variations (50mA–16A) and temperature fluctuations (-40°C to 85°C).