Novel Multi-Spacer Hk/Mg 28 nm Planar MOSFET for Superior Subthreshold Swing and DIBL Optimization: Simulation Design and Process Investigation

This study optimizes 28 nm planar MOSFET technology to reduce device leakage current and enhance switching speed. The specific aims are to decrease subthreshold swing (S.S.) and mitigate drain-induced barrier lowering (DIBL) effect. Silvaco TCAD software is used for process (Athena) and device (Atlas) simulations. For the further development of MOSFET technology, we implemented our device (planar 28 nm n-MOSFET) with high- k metal-gate (HK/MG), lightly doped drain (LDD), multi-spacers, and silicide. Simulation validation shows improvements over other 28 nm devices, with lower static power consumption and notable optimizations in both S.S. (69.8 mV/dec) and DIBL effect (30.5 mV/V).