Investigation of the relationship between threshold voltage shift and power cycling lifetime of SiC MOSFETs

In this study the impact of a long-term threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>) shift on the power cycling (P/C) lifetime of SiC MOSFETs has been investigated. Therefore, comparative P/C tests with pulsed and constant V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> have been carried out, leading to a significantly different amount of V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> shift: The former are usually required to apply the V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SD</inf>(T) -method when power cycling SiC MOSFETs; the latter require a special experimental setup e.g. with on-chip T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf>-sensors, allowing to study this extreme case. Single chip module samples with planar 1200 V SiC MOSFETs and on-chip T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf>-sensor have served as exemplary devices under test Extended data monitoring including ΔV<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> has been applied during all test runs, revealing a much steeper increase at constant gate bias happening mostly within the first cycles of the test run and affecting the lifetime.