Investigation of Gate Driving Condition on p-GaN HEMTs under Single Event Short Circuit Type I

This work investigates the impact of gate driving conditions on the short-circuit withstanding time (SCWT) of Schottky and ohmic gate p-GaN HEMTs under single-event conditions. A modular test setup with low stray inductance (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stray</inf> <15 nH) is developed to evaluate both switching behavior and short-circuit (SC) robustness under uniform test configuration. For the Schottky gate (SG) device, the experimental results indicate that increasing gate resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>) enhances the SCWT at critical DC-link voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</inf> above 350 V) by reducing the peak SC power. In the ohmic gate device, the device switching voltage slope can be well controlled by varying the boost resistance over a wide range. For SC capability investigation, the SCWT at critical V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</inf> exhibits sensitivity to the gate boost current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G,ON</inf>). A trade-off between I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G,ON</inf>, and SCWT is deduced based on the experimental results. Furthermore, three temperature estimation methods are compared for SG device: the Cauer thermal model method, an energy-based calculation method, and using gate leakage current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSS</inf>) as a temperature-sensitive electrical parameter (TSEP). Each method presents its limitations, but all indicate a high junction temperature (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf>) over 300°C during the SC event at nearly failure voltage, signaling critical local temperature behavior.

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Publication Details

Published
2025-08-27
DOI
https://doi.org/10.1109/isps65707.2025.11189935
Primary Topic
GaN-based semiconductor devices and materials
Type
article
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article

Investigation of Gate Driving Condition on p-GaN HEMTs under Single Event Short Circuit Type I

Thomas Basler, Josef Lutz, Maximilian Goller, Gengqi Li
GaN-based semiconductor devices and materials
article

Investigation of Gate Driving Condition on p-GaN HEMTs under Single Event Short Circuit Type I

Thomas Basler, Josef Lutz, Maximilian Goller, Gengqi Li
article en

Abstract

This work investigates the impact of gate driving conditions on the short-circuit withstanding time (SCWT) of Schottky and ohmic gate p-GaN HEMTs under single-event conditions. A modular test setup with low stray inductance (L<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stray</inf> <15 nH) is developed to evaluate both switching behavior and short-circuit (SC) robustness under uniform test configuration. For the Schottky gate (SG) device, the experimental results indicate that increasing gate resistance (R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>) enhances the SCWT at critical DC-link voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</inf> above 350 V) by reducing the peak SC power. In the ohmic gate device, the device switching voltage slope can be well controlled by varying the boost resistance over a wide range. For SC capability investigation, the SCWT at critical V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DC</inf> exhibits sensitivity to the gate boost current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G,ON</inf>). A trade-off between I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G,ON</inf>, and SCWT is deduced based on the experimental results. Furthermore, three temperature estimation methods are compared for SG device: the Cauer thermal model method, an energy-based calculation method, and using gate leakage current (I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GSS</inf>) as a temperature-sensitive electrical parameter (TSEP). Each method presents its limitations, but all indicate a high junction temperature (T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</inf>) over 300°C during the SC event at nearly failure voltage, signaling critical local temperature behavior.

Chemnitz University of Technology (DE)
Openalex Percentile: Top 82%
GaN-based semiconductor devices and materials
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