Predictive Modeling of FPGA Resource and Power Consumption for Configurable CNN Operators

As Convolutional Neural Networks (CNNs) continue to grow in complexity and accuracy, their deployment on embedded platforms requires hardware-aware optimizations to meet stringent constraints on logic resources, power, and latency. FPGAs offer an attractive solution because of their parallelism, reconfigurability, and energy efficiency. However, conventional FPGA design flows remain time-consuming and often lack early-stage estimation capabilities. This work introduces a library of parameterizable Intellectual Properties (IPs) for convolution, activation, and pooling, developed in VHDL and optimized for fixed-point arithmetic. IPs were designed to address various architectural trade-offs involving logic usage, DSP allocation strategy, parallelism, and power efficiency, while also supporting faster development through modular reuse. To accelerate design space exploration, a methodology is proposed for generating predictive mathematical models capable of estimating key FPGA resource metrics as functions of input bit widths. The models were validated with low prediction errors and coefficient of determination (R<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>) values greater than 0.94, allowing accurate estimation of the resources and dynamic power without synthesis. This supports fast architectural decisions and paves the way for automated, resource-aware CNN deployment on FPGAs.