Ultra-Compact Inverse-Designed Integrated Photonic Matrix Compute Core

Leveraging our developed Global–Local Integrated Topology inverse design algorithm, we designed an efficient, compact, and symmetrical power splitter on a silicon-on-insulator platform. This device achieves a low insertion loss of 0.18 dB and a power imbalance of <0.0002 dB between its output ports within an ultra-compact footprint of 5.5 µm × 2.5 µm. The splitter, combined with an ultra-compact 0–π phase shifter measuring only 4.5 µm × 0.9 µm on the silicon-on-insulator platform, forms an ultra-compact inverse-designed integrated photonic matrix compute core, thus enabling the function of matrix operations in optical neural networks. Through a networked cascade of power splitters and phase shifters, this silicon-based photonic matrix compute core achieves an integration density of ~26,000 computational units/mm2. Moreover, it attained 99.05% accuracy in handwritten digit recognition (0–9) and exhibited strong robustness against fabrication errors, maintaining >80% accuracy with >0.9 probability under simulated random fabrication errors.