Symmetry-Aware EKV-Based Metaheuristic Optimization of CMOS LC-VCOs for Low-Phase-Noise Applications

The integration of AI-driven optimization into Electronic Design Automation (EDA) enables smarter and more adaptive circuit design, where symmetry and asymmetry play key roles in balancing performance, robustness, and manufacturability. This work presents a model-driven optimization methodology for sizing low-phase-noise LC voltage-controlled oscillators (VCOs) at 5 GHz, targeting Wi-Fi, 5G, and automotive radar applications. The approach uses the EKV transistor model for analytical CMOS device characterization and applies a diverse set of metaheuristic algorithms for both single-objective (phase noise minimization) and multi-objective (joint phase noise and power) optimization. A central focus is on how symmetry—embedded in the complementary cross-coupled LC-VCO topology—and asymmetry—introduced by parasitics, mismatch, and layout constraints—affect optimization outcomes. The methodology implicitly captures these effects during simulation-based optimization, enabling design-space exploration that is both symmetry-aware and robust to unavoidable asymmetries. Implemented in CMOS 180 nm technology, the approach delivers designs with improved phase noise and power efficiency while ensuring manufacturability. Yield analysis confirms that integrating symmetry considerations into metaheuristic-based optimization enhances performance predictability and resilience to process variations, offering a scalable, AI-aligned solution for high-performance analog circuit design within EDA workflows.