Optimized RSA Hardware Accelerator Design For Blockchain Networks: 2048-Bit Implementation

This paper presents a high-performance computer unit that is intended to serve as a hardware cryptography accelerator for the RSA algorithm. In order to provide robust security and authentication processes, the architecture is designed to accelerate key-pair generation, decryption, and RSA-based encryption—all essential for secure communications. Because RSA uses a lot of processing power, the accelerator allows for faster and more efficient cryptographic processes by relieving the main processor of critical tasks. This system is based on an FPGA platform and uses a FIFO register bank to enable safe and efficient data processing. It implements a data exchange protocol between the RSA acceleration (1024-bit) and the main processor (32-64 bit).The implementation also includes a Pseudo-Random Number Generator (PRNG) to create inputs for An essential step in the creation of RSA keys is the Miller-Rabin primary test. Performance analysis compares software and hardware implementations to demonstrate the advantages of hardware-based RSA acceleration in cryptographic applications. This design contributes to advancements in hardware security solutions by significantly enhancing RSA algorithm efficiency. We enhanced this model from 1024 bits in the KC705 board and developed 2048 bits in the KCU116 KINTEX ULTRASCALE BOARD and improved the 2048-bit cryptographic accelerator, demonstrating greater efficiency, reaching $22.9 \%$, whereas the 1024-bit version achieves 19.5%. However, the 1024-bit design consumes more power at $15 \%$, while the 2048-bit version is more energy-efficient at $\mathbf{8 . 8 \%}$. In terms of latency, the 1024-bit design performs better with a latency of $1 \%$, while the 2048-bit version has a higher latency of $10 \%$. Additionally, the execution time for the 1024-bit accelerator is significantly lower at $\mathbf{0 . 8 \%}$, whereas the 2048-bit version requires more time, measuring $2.107 \%$.