EDA Tool Parameter Optimization Through Fast and Reliable Machine-Learning based Rank Prediction Model

Finding an EDA tool parameter setting that ensures a high-quality final chip is a critical task, but requires an excessive amount of effort and time due to the huge exploration space of tool parameters. In this work, we automate this task by proposing an ML (machine learning) based DSO (design space optimization) approach. In comparison with the conventional ML-based DSO methods, our DSO approach overcomes two critical limitations: (1) the parameter dimension reduction, by which the 1:1 mapping property between the parameter sets of reduced and original (unreduced) dimensions does not hold anymore, and (2) the direct comparison of PPA (power, performance, area) estimates among multiple parameter option combinations, which is unreliable or requires a considerable time in determining new samples of parameter option combination. Precisely, to overcome limitation 1, rather than reducing the parameter set dimension, we develop a mechanism for deriving parameter feature importance, based on which we are able to extract a set of diverse parameter option combination candidates with high potential for achieving better PPA. On the other hand, to overcome limitation 2, instead of computing the PPA estimates directly, we propose an ML-based PPA rank prediction model which predicts if one parameter setting is probabilistically superior/inferior to the other, whose computation is much faster and more accurate than the conventional direct PPA estimate comparison. From our experiments with benchmark designs, it is shown that our approach is able to find samples of design parameter option combinations which are far better than that found by the prior state-of-the-art ML-based approaches, even with fewer design evaluations (i.e., EDA tool runs). In addition, in comparison with the designs produced by using the default parameter option combination, our DSO framework is able to improve the design PPA metrics (i.e., wirelength, worst/total negative time slacks, power consumption, die area) by 5.0% ∼ 45.2%.