On-Chip Decoupling Capacitor Placement with Impedance Constraint for DRAM Design

DRAM circuits are usually without package decoupling capacitors (decaps), and so on-chip power distribution network (PDN) is exposed to package inductances. This entails on-chip decap placement with impedance constraint. Specifically, on-chip PDNs (for both Vdd and Vss) covering DRAM bank and peripheral circuitry (peri, for brevity) are given, while they are connected to a number of package inductances through Vdd and Vss pads; some decaps have been placed in bank area. The problem, which we address, is to place minimum number of peri decaps such that maximum impedance is kept smaller than impedance constraint everywhere in the on-chip PDNsOur solution consists of two components: (1) U-Net for fast impedance prediction. Input maps include the information from PDN strap density, capacitance of decaps, and inductance of power pads. A maximum impedance map at U-Net output is used for impedance constraint check and shows less than 5% error from our experiments. (2) Reinforcement learning (RL) for actual decap placement. A critic is trained to predict Q-value, the cumulative reward from decap placement involving decap count and impedance constraint violations; an actor is trained to locate decaps while such Q-value is maximized. Experiments demonstrate the reduction of decaps by 26% on average of test circuits, with iterative greedy decap placement as a reference.