Low-Power Digital Circuit Design: Evaluating Pass - Transistor Logic and CMOS for Power-Delay Optimization

Energy-efficient digital designs are crucial in modern devices such as IoT and handheld devices. Pass-Transistor Logic (PTL) is a good candidate for designing low-power circuits, but signal loss and voltage level problems still exist. The research employs Cadence Virtuoso to examine and compare PTL and regular CMOS designs of AND, OR, and XOR gates, and a full adder. The evaluation verifies voltagetime waveforms, power consumption, and delays from the $50 \%$ transition points of input and output signals. The findings indicate that PTL consumes less power, but it might not maintain signals clean like CMOS. The research states that PTL can be an excellent candidate for energy-efficient digital circuit design if it is significantly improved. These findings would assist designers wishing to improve performance and power efficiency in modern digital devices.