BeyondPPA: Human-Inspired Reinforcement Learning for Post-Route Reliability-Aware Macro Placement

Macros are pre-designed IP blocks—including memory arrays, analog circuits, and custom accelerators—that occupy large, fixed-shaped regions within a chip layout. Their placement critically impacts system-on-chip (SoC) reliability by affecting power integrity, clock distribution, and signal robustness. Despite advances in commercial EDA tools, macro placement remains a challenging and manual task, often leading to routing congestion, IR drop, and clock skew. While reinforcement learning (RL) techniques show promise, they frequently lack the structural intuition and constraint-awareness seen in expert designs. To bridge this gap, we propose BeyondPPA, a human-inspired RL placement framework that integrates practical layout heuristics into the agent’s reward function—including macro-grid alignment, IO keepout enforcement, corner biasing, and density balancing. These spatial priors guide the agent toward producing more routable and reliable layouts. On the ISPD benchmark suite, BeyondPPA reduces clock latency by up to 21.3%, clock uncertainty by 23.2%, average IR drop by 57.2%, EM violations by 30.4%, and glitch voltage by 9.2× compared to state-of-the-art baselines. These gains highlight that embedding designer-inspired rules into RL not only sustains competitive PPA metrics—achieving 1.43% wirelength and 3.93% congestion reduction—but also significantly improves post-routing reliability, essential for manufacturable SoCs.