A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks

Clock networks are significant contributors to power consumption in modern designs, accounting for approximately 20% of the total power in synchronous circuits. The utilization of pulsed-latch driven by a pulse generator in clock networks has emerged as an effective technique for reducing clock power. However, determining the optimal configuration of pulsed latch and pulse generator groups remains challenging since the complexity combines optimization objectives and physical constraints. This paper presents a novel hybrid optimization framework that combines dynamic programming and reinforcement learning approaches to efficiently optimize low-power pulsed-latch clock networks. We employ dynamic programming to determine the optimal sink latch groups and the type of pulse generator driver as an initial partition of latch groups based on power efficiency and physical constraints. The initial solution provides a strong starting point for the successive reinforcement learning agent, which refines the position of pulse generators while respecting power efficiency and constraints. Evaluations of four modules of an industrial CPU that replace candidate registers ranging from 60,000 to 150,000 demonstrate that our framework achieves power reductions of approximately 16% to 40% over conventional flipflop clock networks with a replacement ratio ranging from 30% to 80%. The framework automatically determines optimal mixed groups of pulsed latches driven by appropriate pulse generators to maximize power efficiency across diverse design contexts.