Adept Domino Logic for Modified Schmitt Trigger Circuits

Schmitt trigger circuit generates square wave to serve as clock signals. The CMOS based designs have gained enormous popularity due to suppressed spikes in the output signal with good packing density. As the technology started to shrink, low power design became a priority. This paper focuses on design of Schmitt trigger circuits with advanced domino logic with integration of low power techniques like clocked delayed dual keeper, foot driven stacked transistor, ground PMOS keeper, high speed domain, leakage control replica keeper, proficient clock delayed dual keeper, etc as schematics in DSCH and the respective layouts in Microwind Tool for technologies like 90nm, 65nm, 45nm and 32nm. The area and power dissipation are measured from HSPICE Tool. From results, it is found that even though the area occupied by proficient Schmitt trigger circuits is slightly more by 1.07% to 2.32%, the power dissipation is less by 7.23%. Also, the leakage current based Schmitt trigger circuits dissipate less power due to design with lesser number of transistors.