Research on Delay-Deterministic Context Switching Techniques for Heterogeneous Multi-Core Systems

In application scenarios with stringent real-time requirements, such as industrial control and edge computing, context switch latency significantly affects system stability and can easily lead to unpredictability in heterogeneous multi-core architectures. This paper proposes a delay-deterministic context switching mechanism tailored for heterogeneous multi-core systems. It establishes a delay modeling framework, designs a “zero-copy” switching path based on full memory protection, and introduces a cross-architecture virtual instruction set (vISA) along with a context encapsulation scheme. The approach integrates TinyML for real-time prediction and incorporates a highprecision monitoring and anomaly detection module. Experiments conducted across x86, ARM, GPU, and FPGA platforms validate the effectiveness of the mechanism. Results show that under high load, the new mechanism reduces latency by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 5 \% - 6 0 \%}$</tex>, stabilizes heterogeneous context switch latency within <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-8 \mu$</tex> s, achieves prediction model errors below 3.1%, and keeps monitoring system response time under 1ms. The proposed mechanism significantly enhances the predictability and real-time performance of context switching, making it well-suited for high-determinism scheduling in complex heterogeneous systems.